For the design of digital circuits on the scale of VLSI (very large scale integration) technology, designers often employ computer aided techniques. Standard languages such as Hardware Description Languages (HDLs) have been developed to describe digital circuits to aide in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL) or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing an integrated circuit with an HDL code, the code is first written and then compiled by an HDL compiler. The HDL source code describes at some level the circuit elements, and the compiler produces an RTL netlist from this compilation. The RTL netlist is typically a technology independent netlist in that it is independent of the technology/architecture of a specific vendor's integrated circuit, such as field programmable gate arrays (FPGA) or an application-specific integrated circuit (ASIC). The RTL netlist corresponds to a schematic representation of circuit elements (as opposed to a behavioral representation). A mapping operation is then performed to convert from the technology independent RTL netlist to a technology specific netlist which can be used to create circuits in the vendor's technology/architecture. It is well known that FPGA vendors utilize different technology/architecture to implement logic circuits within their integrated circuits. Thus, the technology independent RTL netlist is mapped to create a netlist which is specific to a particular vendor's technology/architecture.
One operation, which is often desirable in this process, is to plan the layout of a particular integrated circuit and to control timing problems and to manage interconnections between regions of an integrated circuit. This is sometimes referred to as “floor planning.” A typical floor planning operation divides the circuit area of an integrated circuit into regions, sometimes called “blocks,” and then assigns logic to reside in a block. These regions may be rectangular or non-rectangular. This operation has two effects: the estimation error for the location of the logic is reduced from the size of the integrated circuit to the size of the block (which tends to reduce errors in timing estimates), and the placement and the routing typically runs faster because as it has been reduced from one very large problem into a series of simpler problems.
After placement of components on the chip and routing of wires between components, timing analysis (e.g., timing simulation, or static timing analysis) can be performed to accurately determine the signal delays between logic elements. Back annotation is typically performed to updates a more-abstract design with information from later design stages. For example, back annotation reads wire delay information and placement information from the placement and route database to annotate the logic synthesis design. Back annotated delay information can be used to identify critical paths where the timing requirements are not satisfied; and logic synthesis may be improved to meet the timing requirements.
FIG. 2 shows a flow chart of a typical method to design an integrated circuit. Operation 201 performs logic synthesis to create a logic element network that performs a given set of functions. The logic synthesis operation may transform and restructure the logic to optimize delays, areas and other design goals. The gate-level logic elements are mapped to vendor specific primitives which are placed into various blocks on the chip. Operation 203 places the vendor specific primitives on the chip and routes the wires between the primitives. In place optimizations are typically performed in operation 205 to optimize timing. In place optimizations make constrained changes to the logic elements without significantly changing the placement of the logic elements. Also, in place optimizations can create place and route or design rule violations, which have to be fixed by place and route programs. Essentially, in place optimizations tweak transistor sizes without moving the logic elements around. After operation 207 performs a timing analysis, the earlier stage design from the logic synthesis of operation 201 is back annotated in operation 209. If operation 211 determines that the timing requirements are not satisfied, the design of the logic synthesis may be changed to meet the timing requirements. Alternatively, further in place optimization may be performed to meet the timing requirements.
A typical software program for logic synthesis uses a delay estimator function based on the fanout of a net. Since all logic elements corresponding to a net with a certain fanout are assumed to have the same wire delay, the estimated delay information is not very accurate. Thus, only limited optimizations like resizing or buffering (known as in place optimizations) are typically performed. However, in place optimizations can provide only limited improvements.
In reality the wire delay depends on the length of the wire and route taken from one logic element to the next logic element. There is a higher correlation between placement distance and wire delay than between fanout and wire delay.